Patent · US Active

Techniques in phase-lock loop configuration in a computing device

US10958278B2 · kind B2 · utility

1Cited by

2References

23Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ariel Gur · Atlit, IL
Daniel J. Ragland · Sherwood, US
Yoav Ben-Raphael · Haifa, IL
Ernest Knoll · Haifa, IL

Key dates

Filing date	Jul 31, 2019
Grant date	Mar 23, 2021
Priority date	—
Expiry date	Jul 31, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/50
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.