Vector maximum and minimum with indexing
US10963252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | May 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.