Spatially programmed logic array architecture
US10963302B2 · kind B2 · utility
2Cited by
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19Claims
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Key dates
| Filing date | Mar 22, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | May 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45595
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A spatially programmed logic circuit (SPLC) array system performs spatial compilation of programs for use in the SPLCs to produce standardized compiled blocks representing predetermined portions of an SPLC. The blocks may be freely relocated in an SPLC after compilation by editing of the compiled file. Inter-block communication circuitry allows joining of blocks within an SPLC or across SPLCs to allow scalability and accommodation of different programs with efficient utilization of an SPLC for multiple programs, again without recompilation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.