Synchronization and exchange of data between processors
US10963315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Apr 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprising: a first subsystem comprising one or more first processors, and a second subsystem comprising one or more second processors. The second subsystem is configured to process code over a series of steps delineated by barrier synchronizations, and in a current step, to send a descriptor to the first subsystem specifying a value of each of one or more parameters of each of one or more interactions that the second subsystem is programmed to perform with the first subsystem via an inter-processor interconnect in a subsequent step. The first subsystem is configured to execute a portion of code to perform one or more preparatory operations, based on the specified values of at least one of the one or more parameters of each interaction as specified by the descriptor, to prepare for said one or more interactions prior to the barrier synchronization leading into the subsequent phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.