Minimum input/output toggling rate for interfaces
US10963405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Mar 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for implementing a minimum toggle rate guarantee may comprise first, second, and third circuitries. The first circuitry may calculate a sequence of values for an internal bus inversion signal based upon a sequence of values for a plurality of internal Input/Output (IO) signals. The second circuitry may establish a sequence of values for an external bus inversion signal by selecting between the sequence of values for the internal bus inversion signal and a sequence of substantially random values. The third circuitry may set the values for a plurality of external IO signals to inverted values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a first value, and to values of the plurality of internal signals when respectively corresponding sequence of values for the external bus inversion signal have a second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.