Shift register circuit and its driving method, gate driving circuit and its driving method, and display device
US10964243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Nov 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register circuit according to an embodiment of the present disclosure includes an input sub-circuit and N-stage output sub-circuits. The input sub-circuit is configured to transmit an input signal to a pull up node at a first stage. The output sub-circuit at each stage is configured to transmit a clock signal from a clock signal terminal at a same stage to an output signal terminal at the same stage under the control of a pull-up node at the same stage. The output sub-circuit at each stage is further configured to transmit a signal transmitted to an output signal terminal at the same stage to a pull-up node at an immediately subsequent stage under the control of a shift control signal from a shift control signal terminal at the same stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.