Memory device with strap cells
US10964355B2 · kind B2 · utility
0Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2020 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Jan 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.