Three-port memory cell and array for in-memory computing
US10964362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Apr 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a three-port static random access memory (3P-SRAM) that performs XNOR operations. The cell has a write port and first and second read ports. Read operations are enabled through either the first read port using a first read wordline and a common read bitline or the second read port using a second read wordline and the common read bitline. Read wordline activation is controlled such that only one read wordline is activated (i.e., receives a read pulse) at a time. As a result, a read operation through either read port effectively accomplishes an XNOR operation. Also disclosed is a memory array, which incorporates such cells and which performs XNOR-bitcount-compare functions. Since XNOR-bitcount-compare functions are used in XNOR-NET type binary neural networks (BNNs), the memory array can be employed for implementing such a BNN designed for improved performance, scalability, and manufacturability. Also disclosed is an in-memory computing method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.