Shift register unit, driving method, gate driving circuit and display device
US10964403B2 · kind B2 · utility
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1References
17Claims
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Key dates
| Filing date | May 10, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Jul 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0209
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register unit includes a common circuit and an output circuit. The common circuit is configured to control a potential at a pull-up node under the control of an input end, a resetting end and a first clock signal input end. The output circuit is configured to control 2M gate driving signal output ends to output gate driving signals respectively under the control of the pull-up node, a noise reduction control end and an output control end, where M is an integer greater than 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.