Array substrate, chip on film, and alignment method
US10964644B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Feb 1, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Feb 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54486
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present application provide an array substrate, a chip on film and an alignment method. The array substrate includes a first pin correspondingly connected with a second pin on a chip on film; a first alignment mark located in a preset alignment range of the first pin and aligned with a second alignment mark on the chip on film; and a first offset mark located in the preset alignment range of the first pin, obtained according to the first alignment mark and the second alignment mark and configured to indicate an alignment deviation between the first pin and the second pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.