TFT substrate and manufacturing method thereof
US10964790B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2018 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Oct 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6743
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.