CMOS finFET with doped spacers and method for forming the same
US10964815B2 · kind B2 · utility
0Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2018 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a gate disposed over the substrate, a source/drain disposed in the substrate at two sides of the gate, and an insulating layer disposed over sidewalls of the gate and at least a portion of a surface of the source/drain. In some embodiments, the insulating layer includes a first side facing the gate or the source, and includes a second side opposite to the first side. The insulating layer includes dopants, and a concentration of the dopants is reduced from the second side to the first side of the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.