Delay circuit, clock control circuit and control method
US10965280B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2019 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Dec 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit, a clock control circuit and a control method are disclosed. The delay circuit includes N-stage delay units coupled in a chain, the delay unit of each stage comprises the four-state gate circuit and an inverter circuit, an input terminal of a four-state gate circuit and an input terminal of an inverter circuit of each stage are coupled together, another input terminal of the inverter circuit is coupled to an output terminal of the inverter circuit of the next stage; an input signal is coupled to the input terminal of the four-state gate circuit and the inverter circuit of the first stage, and is output with a certain delay of time by sequentially passing through the four-state gate circuit and the inverter circuit of each stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.