Bit flipping algorithm for decoding LDPC-encoded data
US10965319B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 25, 2018 |
| Grant date | Mar 30, 2021 |
| Priority date | — |
| Expiry date | Nov 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/616
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bit flipping algorithm for an LDPC decoder evaluates a data sequence d with respect to a parity code matrix H. Where one or more checks fail, bits of d are flipped such that for some iterations, the bits are flipped with bias toward and original data sequence r. For example, for some iterations, where the number of failed checks are below a first threshold T1, bits are only permitted to flip back to the value of that bit in the original data sequence r. In such iterations, bits are permitted to flip from the value in the original data sequence r only when the number of failed checks is greater than a second threshold T2, T2>T1. Values for thresholds may be based on a number of flipped bits from a previous iteration and may be calculated using a syndrome s=Hd from a previous iteration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.