Computation engine with upsize/interleave and downsize/deinterleave options
US10970078B2 · kind B2 · utility
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17References
19Claims
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Key dates
| Filing date | Apr 5, 2018 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | May 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a computation engine may perform computations on input vectors having vector elements of a first precision and data type. The computation engine may convert the vector elements from the first precision to a second precision and may also interleave the vector elements as specified by an instruction issued by the processor to the computation engine. The interleave may be based on a ratio of a result precision and the second precision. An extract instruction may be supported to extract results from the computations and convert and deinterleave the vector elements to provide a compact result in a desired order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.