Reducing read-write interference by adaptive scheduling in NAND flash SSDs
US10970204B2 · kind B2 · utility
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Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Dec 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RAID-enabled solid state drive (SSD) including: a controller connected to a plurality of channels; a plurality of flash chip groups, each including a plurality of flash chips coupled to the plurality of channels, the plurality of flash chips including: a plurality of non-parity flash chips; and i parity flash chips, wherein the controller is configured to write data to the plurality of flash chip groups such that within each of the plurality of flash chip groups only i or less flash chips of the plurality of flash chips are allowed to be written to at the same time, where i is an integer equal to 1 or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.