Information processing apparatus, ising device, and information processing apparatus control method
US10970361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2017 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Feb 6, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Arithmetic circuits calculate d−1 energy values (hi2 to hid) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.