Calculating and extracting Joule-heating and self-heat induced temperature on wire segments for chip reliability
US10970437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2020 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Jan 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.