Power saving display having improved image quality
US10971085B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Jan 8, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure is directed to systems and methods of optimizing display image quality on display devices having a plurality of display power modes. Each power mode has associated therewith a respective baseline allowable percentage of distorted pixels and a baseline first relationship between an original pixel value and boosted pixel value. Display control circuitry determines a baseline second relationship using the baseline percentage of distorted pixels and the baseline first relationship. The display control circuitry selects a plurality of test distorted original pixel values and determines a respective test first relationship. Using the test distorted original pixel value, the respective test first relationship, and the baseline second relationship, the display control circuitry determines a respective PSNR and value indicative of the change in display image quality for each of the test distorted original pixel values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.