Semiconductor package structure
US10971475B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 6, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Aug 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.