Pixel array and fabrication method thereof
US10971523B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 7, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | May 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0876
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a pixel array and a fabrication method thereof. The pixel array includes a plurality of gate lines and a plurality of data lines which are arranged intersected and insulated and a pixel unit disposed at a position where each of the plurality of gate lines and each of the plurality of data lines are intersected. The pixel unit includes a thin film transistor (TFT). The width-to-length ratios of channels of the TFTs are sequentially increased in such a manner that the width-to-length ratios of the channels of the TFTs in the pixel units positioned in a same row (and/or a same column) are sequentially increased along a scanning direction of the gate line coupled to gate electrodes of the TFTs in the same row (and/or along a data writing direction of the data line coupled to the source electrodes of the TFTs in the same column).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.