Method for manufacturing semiconductor device
US10971606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Jul 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
Abstract
A method for manufacturing a semiconductor device includes forming a shallow trench isolation (STI) structure surrounding a pair of semiconductor fins; forming a dummy gate layer over the STI structure and the semiconductor fins; etching a first portion of the dummy gate layer to form a trench through the dummy gate layer until the STI structure is exposed, in which the trench extends between the semiconductor fins along a lengthwise direction of the semiconductor fins; forming an insulating structure in the trench through the dummy gate layer; after forming the insulating structure extending through the dummy gate layer, patterning the dummy gate layer to form a pair of dummy gate structures each of which is across a respective one of the semiconductor fins; and replacing the dummy gate structures with a pair of metal gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.