Process-invariant delay cell
US10972068B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2018 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Feb 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2001/0064
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.