Wireless networking transceiver system with shared memory
US10972142B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Dec 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/38
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Wireless networking transceiver circuitry for an integrated circuit device includes a plurality of wireless networking transceiver subsystems, each subsystem including respective processing circuitry configurable for coupling to radio circuitry to implement a respective set of protocol features selected from at least one overall set of protocol features. Memory circuitry is provided, sufficient to support a respective set of protocol features in each subsystem when at least one respective set of protocol features is smaller than the overall set of protocol features. Memory-sharing circuitry is provided, configurable to couple respective portions of the memory circuitry to the processing circuitry of respective subsystems. The memory circuitry and the memory-sharing circuitry may be outside the subsystems, or distributed within the subsystems. The memory may be 60% of an amount of memory sufficient to support the overall set of protocol features in all subsystems. Each processing circuit may be coupled to radio circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.