Method of calibrating clock phase and voltage offset, data recovery circuit performing the same and receiver including the same
US10972248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2019 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Dec 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0087
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.