Clockless decision feedback equalization (DFE) for multi-level signals
US10972319B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2018 |
| Grant date | Apr 6, 2021 |
| Priority date | — |
| Expiry date | Sep 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4917
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.