Two pin scan interface for low pin count devices
US10976366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2018 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Oct 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31727
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan controller provides a translation between a two terminal external interface and a four signal line internal scan interface to a digital core of the integrated circuit. The two terminal external interface has an input terminal and an input/output terminal. The input terminal receives a clock signal and the input/output terminal serially receives a scan enable signal and a scan in data bit. A state machine controls the scan controller. The scan in data bit, the scan enable signal, and a scan clock signal are supplied in parallel to the internal scan interface. The digital logic provides a scan out data bit and the scan controller supplies the scan out data bit over the input/output terminal in synchronism with the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.