Instruction completion table with ready-to-complete vector
US10977034B2 · kind B2 · utility
0Cited by
13References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2018 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Jan 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method, computer program product, and computer processing system are provided. The method includes processing, by a superscalar processing pipeline, respective sets of instructions in respective instruction processing cycles using an Instruction Completion Table (ICT) with a Ready-To-Complete (RTC) vector. The ICT includes a plurality of entries, each corresponding to a respective one of the instructions. A Next-To-Complete (NTC) instruction from among the respective sets of instructions is computed using the RTC vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.