Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
US10977039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Nov 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed doubleword data elements; a second source register to store a second plurality of packed doubleword data elements; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply a first doubleword data element from the first source register with a second doubleword data element from the second source register to generate a first quadword product and to concurrently multiply a third doubleword data element from the first source register with a fourth doubleword data element from the second source register to generate a second quadword product; and a destination register to store the first quadword product and the second quadword product as first and second packed quadword data elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.