System for and method of manufacturing an integrated circuit
US10977421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2020 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Feb 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.