Semiconductor package
US10978432B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor package, a second semiconductor package on the first semiconductor package, and a plurality of connection terminals between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a package substrate, a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package, a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals, and a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.