Vertical non-volatile memory device with high aspect ratio
US10978464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2020 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | May 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.