Array substrate and method of manufacturing the same, and display device
US10978495B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | May 9, 2018 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Aug 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate includes an electrostatic shielding layer disposed on a substrate, an isolating layer covering the electrostatic shielding layer, gate lines, data lines, and thin film transistors. The gate lines, the data lines, and the thin film transistors are disposed on the isolating layer. An orthographic projection of a pattern of the electrostatic shielding layer on the substrate covers an orthographic projection of at least one of a pattern of the gate lines, a pattern of the data lines, and a pattern of the thin film transistors on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.