Scalable synthesis of signals of high symbol rate using lower symbol rate DSPS
US10979270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Mar 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/26362
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for transmitting signals with a high data rate. In some implementations, an apparatus includes a first digital signal processor outputting first data at a first data rate. A second digital signal processor outputting second data at a second data rate. A filter circuitry receiving and up-sampling the first and second data. Additionally, the apparatus includes a combiner circuit that receives the first up-sampled data and the second up-sampled data, the combiner circuit combining the first and second up-sampled data to provide a multiplexed output, the multiplexed output having a third data rate that is greater than the first data rate or the second data rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.