Generating design verification test cases using a restricted randomization process based on variable dependencies
US10984158B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2020 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Mar 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for generating design verification test cases using a restricted randomization process are provided. According to one embodiment, a processor of a hardware design verification system receives a set of restrictions and defines a scenario involving the values that is to be excluded from the test case. The processor also receives pre-assigned values for one or more variables. For each variable other than the one or more variables, the processor assigns a first random value to the variable that is within a valid range for the variable. The processor then identifies a conflict between a first pair of variables, and resolves the conflict by assigning a second random value to a first variable or a second variable of the first pair of variables within their respective valid ranges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.