Gate driving circuit
US10984748B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Jun 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3677
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This disclosure provides a gate driving circuit, which comprises: first P-channel, second P-channel, first N-channel and second N-channel transistors, each has a gate, a source, a drain, and a base connected to the source; an output terminal electrically connected to the drains of the second N-channel and P-channel transistors; wherein the source of the first P-channel transistor is connected to a first voltage source, and a first voltage is applied to its gate; the source of the first N-channel transistor is connected to a second voltage source, and a second voltage is applied to its gate; the source of the second P-channel transistor is connected to the drain of the first P-channel transistor, and a third voltage is applied to its gate; the source of the second N-channel transistor is connected to the drain of the first N-channel transistor, and a control voltage is applied to its gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.