Superconductive memory cells and devices
US10984857B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2019 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Sep 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device (e.g., a superconducting memory cell) includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material is patterned to form a plurality of distinct instances of the layer of superconducting material including: a first wire; and a loop that is (i) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state. The loop is configured to form a persistent current via the capacitive coupling in response to a write current applied to the first wire while the loop and the first wire are in the superconducting state. The persistent current represents a logic state of the electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.