Non-volatile memory device and method of erasing the same
US10984871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2020 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Aug 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a memory cell region including a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad; a substrate in the memory cell region; a memory cell array in the memory cell region comprising a plurality of gate conductive layers stacked on the substrate and a plurality of pillars penetrating through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the substrate, wherein at least one of the plurality of gate conductive layers is a ground select line; a control logic circuit in the peripheral circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array; a substrate bias circuit in the peripheral circuit configured to, in response to the erase enable signal, output a substrate bias voltage at a first target level to the substrate from a first time to a second time after the first time during a first delay period and, after the first delay period gradually increase a level of the substrate bias voltage to an erase voltage …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.