Semiconductor device
US10985275B2 · kind B2 · utility
1Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2019 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Jul 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.