Method for biasing a differential pair of transistors, and corresponding integrated circuit
US10985750B2 · kind B2 · utility
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6References
24Claims
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Key dates
| Filing date | May 28, 2020 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | May 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.