Method of calibrating capacitive array of successive approximation register analog-to-digital converter

US10985771B2 · kind B2 · utility

Assignee

• University of Electronic Science and Technology of China · CN

Inventors

• Hua Fan · Chengdu, CN
• Chen Wang · Beijing, CN
• Peng Lei · Redmond, US
• Dainan Zhang · Chengdu, CN
• Quanyuan Feng · Chengdu, CN
• Lang Feng · New York, US
• Xiaopeng Diao · Chengdu, CN
• Dagang Li · Chengdu, CN
• Kelin ZHANG · Foshan, CN
• Daqian Hu · Chengdu, CN
• Yuanjun Cen · Chengdu, CN

Key dates

• Filing date: Dec 4, 2019
• Grant date: Apr 20, 2021
• Expiry date: Dec 4, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M1/804
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2M−1; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors Cu(n/2)*, Cu(n/2+1)* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR ADC.