System, apparatus and method for loose lock-step redundancy power management
US10990154B2 · kind B2 · utility
1Cited by
25References
20Claims
0Family size
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Key dates
| Filing date | Oct 25, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Oct 25, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.