Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator
US10990397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Oct 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses relating to a matrix operations accelerator are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of fused multiply accumulate circuits; a first plurality of registers that represents an input two-dimensional matrix coupled to the matrix operations accelerator circuit; a decoder, of a core coupled to the matrix operations accelerator circuit, to decode an instruction into a decoded instruction; and an execution circuit of the core to execute the decoded instruction to cause the two-dimensional grid of fused multiply accumulate circuits to form a transpose of the input two-dimensional matrix when the matrix operations accelerator circuit is in a transpose mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.