Call/return stack branch target predictor to multiple next sequential instruction addresses
US10990405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Mar 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a branch detection module and a branch predictor module. The branch detection module determines that a first program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a first routine branch is a possible return capable branch having the first routine instruction address that is a detected as being offset. The branch predictor module determines that a second program branch is a possible call branch having a next sequential instruction address (NSIA), and determines that a second routine branch is a predicted return branch having a predicted target instruction address based on the NSIA of the second program branch and the predicted offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.