Memory controller and operating method thereof
US10990523B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Nov 15, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller configured to control a memory device including a plurality of banks. The memory controller may determine whether a number of write commands enqueued in a command queue of the memory controller exceeds a reference value, calculate a level of write power to be consumed by the memory device in response to at least some of the write commands from among the enqueued write commands when the number of enqueued write commands exceeds the reference value, and schedule, based on the calculated level of write power, interleaving commands executing an interleaving operation of the memory device, from among the enqueued write commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.