System and method for coping with fault injection attacks
US10990682B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Jan 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2137
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A security system dynamically, depending on processor core execution flow, controls fault injection countermeasure circuitry protect processor core from fault injection attacks. Includes a processor core which, when in use, executes instructions and concurrently, generates, in real time, output indications of instructions to be executed; a fault injection detector having selectable sensitivity levels; and a sensitivity level control module operative, in real time, to receive the output indications, select a next sensitivity level using sensitivity level selection logic which receives the output indications as inputs, and set the fault injection detector to the next sensitivity level, thereby to provide fault injection countermeasure circuitry which is differentially sensitive, when protecting the processor core from fault injection attacks, depending on the output indications of the instructions, and/or avoids false alarms which would result if processor core protection were provided at a sensitivity level unrelated to the output indications of the instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.