Method and apparatus for integrated circuit mask patterning
US10990744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2018 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Aug 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/70
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.