Memory-in-pixel circuit and driving method thereof, and liquid crystal display panel including the same
US10991333B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 6, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Nov 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0281
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory in-pixel (MIP) circuit, a driving method of the MIP circuit, and an LCD panel fabricated using the MIP circuit. The MIP circuit comprising an input circuit, a control circuit and an output circuit. The input circuit brings the first input terminal and the second input terminal into conduction with a first node and a second node respectively in response to the first control signal of the first control terminal being active. The control circuit is configured to set and maintain the potential of a third node or a fourth node active based on the potential of the first node and the second node. The output circuit is configured to bring the output terminal into conduction with the first or second input terminal according to the potential of the third and the fourth node in response to the second control signal of the second control terminal being active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.