Active matrix substrate and method for producing same
US10991725B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2018 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Mar 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An active matrix substrate includes: a substrate (1); a peripheral circuit including a plurality of first TFTs (10); and a plurality of second TFTs (20), wherein each of the first and second TFTs (10, 20) includes: a gate electrode (3A, 3B); a gate insulating layer (5); an oxide semiconductor layer (7A, 7B) including a channel region (7Ac, 7Bc), a source contact region (7As, 7Bs) and a drain contact region (7Ad, 7Bd), wherein the source contact region and the drain contact region are located on opposite sides of the channel region; a source electrode (8A, 8B) that is in contact with the source contact region and a drain electrode (9A, 9B) that is in contact with the drain contact region; the oxide semiconductor layer of the first TFTs and the second TFTs is formed from the same oxide semiconductor film; a carrier concentration in the channel regions (7Ac) of the first TETs is higher than a carrier concentration in the channel regions (7Bc) of the second TETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.