Amplifier with input bias current cancellation
US10992271B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Jul 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/411
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier includes a first input transistor, a second input transistor, a first cascode transistor, a second cascode transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal and the first input transistor. The first cascode transistor is coupled to the first input transistor. The second cascode transistor is coupled to the second input transistor and the first cascode transistor. The first current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the first input terminal. The second current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the second input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.